Over the years, in the field of integrated circuits, it has been recognized that the manufacturing cost of a given integrated circuit is largely dependent upon the chip area required for implementation of a desired function. Accordingly, the geometries and sizes of active components, such as the gate electrode in metal-oxide-semiconductor ("MOS") technology, are important elements in defining the chip area for a given integrated circuit. These geometries and sizes, in turn, are often dependent upon the photolithographic resolution available for a particular manufacturing facility.
As the degree of integration has advanced over the years, however, it has been recognized that it is desirable to minimize the topographical excursion of the surface at each level, especially the upper levels. To accomplish this, various planarization techniques have been developed to planarize the interlevel dielectric. Some of these, for example, include chemical-mechanical-polishing ("CMP"), use of permanent spin-on-glass ("SOG"), e.g., left in place in the final chip, and sacrificial etchback SOG.
SOG deposition has been used in the semiconductor industry for many years. The unprocessed SOG material is a fluid or gel-like material. After the fluid material is coated onto the face of a wafer, the wafer is rotated at high speed to throw off or discard the excess material. The surface tension and adhesion of the material provides a generally flat or substantially planarized surface with a controlled thickness. The fluid material is then baked in order to drive off solvents and provide a stable solid silicate glass.
An example of pre-metal planarization can be seen in U.S. Pat. No. 5,395,785 by Nguyen et al. titled SRAM Cell Fabrication With Interlevel Dielectric Planarization." This patent describes a method wherein planarization of a static random access memory ("SRAM") cell is performed before metal formation and before resistor formation. The pre-metal planarization utilizes a sandwich structure having permanent SOG, undoped glass, and permanent SOG. The undoped glass is used as a buffer layer between two layers of SOG to prevent SOG cracks. The double SOG enhances the degree of planarization.
Another factor in the chip area required for integrated circuits is the isolation technology. Sufficient electrical isolation must be provided between active circuit elements so that leakage therebetween does not cause functional or specification failure. The isolation is particularly important for circuits such as SRAMs where maintenance of stored data by extremely low levels of standby current has become highly desirable. Because the presence of leakage between active regions in the memory will greatly increase the standby current drawn, such low standby currents require excellent isolation. This increasingly difficult standby current requirement or desirability, in combination with the demand for smaller and smaller memory cells in denser memory array, forms increased pressure on the isolation technology in SRAMs and other integrated circuits.
A known isolation technique, for example, is local oxidation of silicon ("LOCOS"). In LOCOS, an oxidation barrier is placed over the locations of the surface of the chip into which the active devices are to be formed, i.e., active regions. The wafer is then placed in an oxidizing environment. The portions of the wafer surface not covered by the oxidation barrier oxidize to form thermal silicon dioxide. Oxidation is masked from the active regions by the oxidation barrier. LOCOS field oxide is generally formed to a sufficient thickness that a conductor placed thereover will not invert the channel thereunder, when biased to the maximum circuit voltage. LOCOS, however, is subject to certain known limitations, including encroachment of the oxide into the active regions due to oxidation of silicon under the edges of the nitride mask and the adding of topography to the integrated surface.
A more recently known isolation technique uses trenches etched into the surface of the wafer at the isolation locations. The trenches are then filled with a thermal or deposited oxide. Such trench isolation can provide extremely thick isolation oxides which extend into the wafer surface with little or no encroachment. Etching of deep trenches, however, can be a relatively expensive process and can be quite difficult to perform when attempting to maintain close geometries. Also, thermally formed silicon dioxide, for example, generally has a higher integrity than deposited silicon dioxide. The formation of thermal silicon dioxide trenches, however, causes stress in the silicon due to volume expansion of silicon dioxide from that of the silicon prior to oxidation. Accordingly, trench isolation tends to largely rely on deposited oxide.
Even more recently, integrated circuits with planarized shallow trench isolation ("STI") have been developed such as seen in U.S. Pat. Nos. 5,130,268 and 5,410,176 each by Liou et al. and respectively titled Method For Forming Planarized Shallow Trench Isolation In An Integrated Circuit And A Structure Formed Thereby" and "Integrated Circuit With Planarized Shallow Trench Isolation." After formation of the recesses, sidewall filaments of insulating material, such as silicon dioxide, are formed into some or all of the recesses thereby exposing the bottom silicon portion thereof. Selective epitaxy then forms a silicon layer within the recesses from the bottom up, but not along the sides or sidewalls. The selective epitaxial layer is oxidized so that the recesses are substantially filled with thermal silicon dioxide. Both recesses with vertical sidewalls, formed by anisotropic etching of the silicon, or sloping sidewalls, formed by more isotropic silicon etching, can be utilized.
One of the key processes for STI is planarization after trench fill. The conventional methods generally require some type of inverse active pattern, resist/oxide etchback, resist strip, and CMP to complete the planarization process. These planarization process requirements, however, may not provide the consistent results desired. For example, the resulting integrated circuits using CMP for the planarization process can result in erosion of the corners extending along peripheral regions of the trench and can result in dishing along the upper surface of the filled trench.